Fluidic self-assembly is a fabrication process whereby individual device microstructures are integrated into receptacle sites on host electronic circuits using a liquid medium for transport. Placement and registration of the device microstructures into receptacles on a substrate carrying electronic microcircuits is controlled by shape recognition or by selective chemical adhesion or both.
Methods for fabricating device microstructures by fluidic self-assembly are known in the art. U.S. Pat. No. 5,545,291, which is incorporated herein by reference, describes one such method comprising the steps of providing a plurality of shaped blocks, each shaped block comprising an integrated circuit device thereon; transferring said shaped blocks into a fluid to form a slurry; and    dispensing said slurry over a substrate at a rate where at least one of said shaped blocks is disposed into a recessed region in the substrate. In the '291 patent, the substrate is selected from a group consisting of a silicon wafer, plastic sheet, gallium arsenide wafer, glass substrate, and ceramic substrate. The rate is substantially a laminar flow and allows each of the shaped blocks to self-align into said recessed region.
In the '291 patent, the blocks comprising the integrated circuit device thereon are shaped by masking and etching. With reference to FIGS. 1–3 of the attached drawings, a block substrate 2 is provided with a top layer 4, a bottom layer 6 and a sacrificial layer 8 atop the top surface 9 of the bottom layer 6 (FIG. 1). The blocks are shaped by masking and etching the top layer using known techniques to form the etched block substrate shown in FIG. 2 comprising photoresist layer 10 atop shaped blocks 12. Then, the shaded blocks 12 are removed by preferential etching of sacrificial layer 8 (FIG. 3). The removed blocks 12 (FIG. 3) are then mixed with an inert fluid to form a slurry and the slurry is deposited on the top surface of a substrate comprising recessed regions to allow the blocks to self-align in the recessed regions of the substrate.
To insure proper placement and registration of the microstructures in the recessed regions, the recessed regions in the prior art substrates have been etched to provide receptacle sites with geometric profiles that are complementary to the profiles of the blocks. Receptacle sites in other reports of fluidic self-assembly have also been made by etching recesses in the surface of silicon substrates. Single crystalline silicon can be etched by a number of methods to produce a variety of sidewall profiles. The etching behavior of most wet-processes can be categorized as isotropic or crystallographic. Receptacles fabricated using crystallographic etches are the most favorable for forming receptacle sites.
An SEM photograph of a cystallographically etched receptacle in Si (100) using an aqueous KOH solution is shown in FIG. 4. The KOH etch generates recesses whose sidewalls are formed along (111) planes. It is difficult to produce complementary shapes between receptacles and device microstructures using this approach because the microstructures require an exterior surface etch and the receptacles require an interior surface etch. The best results for shape matching have been achieved using corner compensation masking techniques for etching the device microstructure. This technique prevents the corners from being rounded (which is observed in the microstructures in FIG. 4). In general the microstructures (outside etch) are found to be etched with a more tapered shape than the receptacle sites. This leads to a loose fit. Evidence of poor shape matching between the wet-etched microstructure devices and the Si receptacles is seen in FIGS. 4 and 5. This mismatch has been reported by other researchers in fluidic self-assembly.
An alternative method for forming receptacles in polymer surfaces is plasma etching. There have been a number of reports in the literature for forming tapered holes in polyimide. The methods for forming the tapered sidewalls involve using specially prepared photoresist masks (tapered erosion masks). These methods are typically limited to several microns of depth because the masking material and the polymer etch at the same rate. Producing asymmetric receptacles (i.e. those with different sidewall profiles) is impractical using plasma etching. Thus, forming receptacles by plasma etching for fluidic self-assembly applications is restricted to symmetric structures of limited depth.
It may be appreciated from the above that an improved method is needed to form substrates with arrays of recessed receptacle sites that precisely match the shape of particular device microstructures.